IET Prize 2026 • CapstoneVAIDAR: AI-Driven Hardware-in-the-Loop FPGA Verification
Python-native HIL execution engine for AMD Xilinx Artix-7 FPGA silicon with PyTorch & LLM-driven stimulus synthesis and automated failure triage.
Engineering Portfolio
Projects & Technical Systems
Hardware-in-the-loop testbeds, FPGA digital architectures, autonomous robotics, low-level firmware libraries, and telecommunications simulations built across academia and industry.
Flagship Engineering Projects
Detailed project breakdowns with hardware schematics, physical silicon testbeds, and source code repositories.
IET Prize 2026 • Capstone
RTL Logic & FSM SynthesisVHDL Digital Systems & FPGA Logic Design
Modular digital logic and FPGA hardware description library in IEEE VHDL: multi-floor elevator FSM, synchronous request queue, 2's complement ALU, and registers.
WAN & RF Sensing ArchitectureData Communications & Multi-Site WAN Network Architecture
Hierarchical WAN topology in Cisco Packet Tracer: Layer 3 serial routing (V.35 DTE/DCE), WPA2-PSK wireless infrastructure, IoT automation, and RF Sensing / CSI analysis.
Virtual Instruments & DSPMATLAB Engineering Suite: Telemetry Apps, DSP Filters & Simulink
Interactive App Designer telemetry instruments, PIC16F84A opcode explorer, Bilinear Transform filter synthesis, Simulink audio pipeline, and HDL export.
Autonomous Robotics & SensorsAutonomous Mobile Sensor Buggy & Dual-Display Embedded C System
Autonomous corridor navigation buggy powered by dual PIC16F873 microcontrollers, dual I2C LCD telemetry displays, ADC thermistor calibration, and HC-SR04 ultrasonic sonar evasion.
2nd Place Podium FinishAutonomous Combat Robotics Platform & Motor Controller
High-current dual H-bridge motor driver schematic, ultrasonic sonar ranging, and embedded C firmware. 2nd Place Winner in University Robot Wars tournament.
Cycle-Accurate MPASM AssemblyLow-Level PIC Microcontroller Assembly (MPASM) Library
Cycle-accurate MPASM assembly routines for Microchip PIC16F873 and PIC16F84A: hardware UART command reception, Timer 2 register control, and dynamic PWM duty cycle modulation.
Brighton Real Ale Society Web Platform & Member System
Full-stack web application with Next.js App Router, Prisma ORM, and Supabase PostgreSQL hosting real-time leaderboards, voting, and society history.
Technical Competencies
Engineering Disciplines & System Capabilities
Key engineering capabilities and verified technical outcomes demonstrated across physical hardware, digital logic, and software automation.
FPGA & Hardware Verification
Silicon ValidationPhysical silicon Hardware-in-the-Loop testbeds streaming automated Python stimulus into physical AMD Xilinx Artix-7 and Intel Cyclone FPGAs at 968.9 tests/second. Automated anomaly triage, timing closure, and Vivado/ModelSim verification.
Key Technical Outcomes
- 968.9 tests/sec physical throughput across 921,600 baud serial bridge
- Automated discrepancy triage comparing physical silicon against golden reference models
- RTL state machines, 16-bit ALU datapaths, and synchronous arbitration queues in Verilog & VHDL
Autonomous Robotics & Control
Hardware & FirmwareEmbedded C control software, multi-microcontroller distributed architectures, and custom discrete motor drivers for autonomous corridor-navigating platforms and combat robotics.
Key Technical Outcomes
- 2nd Place podium finish in inter-collegiate combat robotics arena tournament
- Dual PIC microcontroller task partitioning with calibrated ADC thermistor and sonar evasion
- High-current MOSFET H-bridge motor controllers with PWM speed modulation
Low-Level Firmware & Microprocessors
Cycle-Accurate AssemblyBare-metal assembly firmware targeting Microchip PIC microcontrollers. Direct hardware register manipulation, interrupt-driven peripherals, and full-duplex communication protocols.
Key Technical Outcomes
- Cycle-accurate MPASM assembly routines for PIC16F873 and PIC16F84A
- Full-duplex master-slave communications bus and parallel display latching
- Timer 2 register configuration and CCP1 module PWM duty modulation
Telecommunications & Networking
Network ArchitectureMulti-site WAN topological design, enterprise routing architectures, wireless network infrastructure, and radio frequency sensing research.
Key Technical Outcomes
- Layer 3 hierarchical WAN routing with V.35 serial DTE/DCE topologies in Cisco Packet Tracer
- WPA2-PSK enterprise wireless infrastructure and IoT event-triggered automation
- Channel State Information (CSI) evaluating human presence sensing using Software-Defined Radios
Virtual Instrumentation & DSP
Signal ProcessingCustom interactive desktop telemetry applications, digital filter synthesis, and dynamic audio processing pipelines in MATLAB and Simulink.
Key Technical Outcomes
- Dual-channel real-time desktop oscilloscope turning external microcontrollers into lab instruments
- 11th-order Butterworth IIR and 324th-order Hamming FIR filter synthesis with Bilinear Transformation
- Dynamic 3-band audio crossover and synthesiseable RTL IP core export via HDL Coder
Academic Credentials & Transcripts
Looking for Year-by-Year Academic Grades?
All 17 university module marks across all three years, First-Class Honours (80%) classification, and The IET Prize 2026 citation are comprehensively documented in the Curriculum Vitae.