Biography
My Background
I’m a Hardware Test Engineer at Chess Dynamics in West Sussex, verifying military-grade electro-optical tracking directors and stabilised gimbal systems for international defence programmes.
I spend a lot of my time working with FPGAs and digital logic. For my final-year project, I built an automated hardware-in-the-loop test framework to verify physical Xilinx FPGAs against golden models using Python.
I graduated from the University of Brighton with a First Class 80% degree in Electronic & Computer Engineering, and was awarded the IET Prize in 2026.
Before joining Chess, I spent a year at BAE Systems working on integration and automated testbenches for electronic systems.
Academic Honours & Awards
- The IET Prize (2026)The Institution of Engineering and Technology
Awarded for exceptional academic excellence and First Class 80% performance in BEng Electronic & Computer Engineering at the University of Brighton.View Official Certificate ↗
- IET Sussex Prize (2023)The Institution of Engineering and Technology
Professional Philosophy
Good hardware testing is about catching failure modes early with reliable automation. Whether I'm testing electro-optical directors on defence rigs or writing FPGA testbenches, I focus on building clear, reproducible test environments.