VHDL Digital Systems & FPGA Logic Design

Project Overview

A modular digital logic and FPGA hardware description library written in IEEE standard VHDL, developed for the Digital Systems Design curriculum at the University of Brighton and earning a First Class 84% (A+).

The repository implements synchronous finite state machines (FSMs), priority request arbitration queues, arithmetic sub-units (ALUs, ripple adders, multipliers, magnitude comparators), sequential shift registers, and seven-segment display decoders synthesised in Intel Quartus Prime and verified through gate-level timing simulations in ModelSim.

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Physical FPGA Hardware Testbed

The flagship multi-floor elevator controller was compiled onto an Altera/Intel Cyclone FPGA and deployed to a physical hardware testing harness consisting of tactile floor call switches, emergency stop buttons, and LED position indicators:

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ModelSim Timing Simulation & Verification

Prior to silicon programming, the complete digital architecture underwent cycle-accurate timing simulation in ModelSim to verify setup/hold slack, asynchronous reset handling, and state transition latency:

Figure 1: ModelSim functional and timing waveform trace illustrating clock edge alignment, floor queue arbitration, door open/close timeouts, and state register transitions.

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Architecture Specifications: Multi-Floor Elevator Controller

Subsystem Module	Entity Name	Description	Key Signals
Main FSM Controller	Lift.vhd	Finite state machine coordinating motor direction, floor arrival, and door sequencing.	clk, reset, floor_req, motor_up, motor_down, door_open
Synchronous Queue	Queue.vhd	FIFO/priority queue latching external floor calls and scheduling the shortest path.	req_in, serviced, next_target
Door Actuator	doors_but_better.vhd	Timed door cycle controller with safety obstacle pause and auto-retract.	door_sensor, timer_done, door_state
Clock Prescaler	clock_div1.vhd	Integer clock divider converting 50 MHz FPGA system clock down to 1 Hz visual update pulses.	clk_50MHz, clk_1Hz
Display Decoder	bin2hex.vhd	4-bit binary to active-low 7-segment hex character mapping.	data_in[3:0], seg_out[6:0]

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VHDL Finite State Machine Implementation

The core elevator logic is structured as a two-process synchronous FSM separating combinatorial next-state logic from clocked sequential state registers:

Figure 2: Carbon-style syntax-highlighted IEEE VHDL listing defining the finite state enumeration (IDLE, MOVING_UP, MOVING_DOWN, DOOR_OPEN), clock synchronisation process, and next-state transition logic.

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Arithmetic & Sequential Building Blocks

In addition to the elevator system, the repository contains a library of synthesiseable digital logic primitives:

1. Original RTL by Harry Rogers

• bitMultip.vhd: Combinational 2-bit binary multiplier array.
• Comp4.vhd: 4-bit unsigned magnitude comparator ($A > B$, $A = B$, $A < B$).
• Sub4.vhd: 4-bit dedicated binary subtractor.
• full_adder_vhdl_code.vhd: Structural 1-bit full adder primitive with carry propagation.
• bin2hex.vhd: 4-bit binary to 7-segment hex display decoder.
• clock_div1.vhd: Synchronous integer clock frequency prescaler.

2. University Coursework Reference Modules (Designed by Chris Knight)

• Adder_Sub.vhd: Selectable ripple-carry adder/subtractor provided as laboratory coursework reference material.
• Counter.vhd & CounterTB.vhd: Synchronous up/down counter reference implementation.
• ShiftReg1.vhd: 4-bit shift register reference implementation.

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Source Code & Academic Attribution

• GitHub Repository: HarryRogers073/vhdl-digital-systems
• Author: Harry Rogers (University of Brighton)
• Coursework Context: Digital Systems Design (First Class 84%, A+)
• Synthesis & P&R: Intel Quartus Prime Lite / Standard Edition
• Simulation: ModelSim-Intel FPGA Starter Edition
• Hardware Target: Altera / Intel Cyclone II / IV / DE2 Development Boards